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integrated circuit systems, inc. ics953002 0924?11/18/09 pin configuration recommended application: chipset for p4 type processor with pci-express output features: 2 - 0.7v current-mode differential cpu pairs 1 - 0.7v current-mode differential cpu/pci-express selectable pair 6 - pci, 33mhz 2 - ref, 14.318mhz 3 - 3v66, 66.66mhz 1 - 48mhz 1 - 24/48mhz 5 - pci-express 0.7v current mode differential pairs key specifications: cpu outputs cycle-cycle jitter < 85ps 3v66 outputs cycle-cycle jitter < 250ps pci outputs cycle-cycle jitter < 500ps programmable timing control hub? for next gen p 4 ? processor functionality features/benefits: programmable output frequency. programmable asynchronous 3v66&pci frequency. programmable asynchronous pci-express frequency. programmable output divider ratios. programmable output skew. programmable spread percentage for emi control. watchdog timer technology to reset system if system malfunctions. programmable watch dog safe frequency. support i2c index read/write and block read/write operations. uses external 14.318mhz reference input, external crystal load caps are required for frequency tuning. advance information documents contain information on products in the formative or design phase development. characteristic data and other specific ations are design goals. ics reserves the right to change or discontinue these products without notice. third party brands and names are the property of their respective owners. b0b4 b0b3 b0b2 b0b1 b0b0 pci-ex agp pci cpu fs4 fs3 fsl2 fsl1 fsl0 mhz mhz mhz mhz 00 0 0 0 100.00 66.66 33.33 266.66 00 0 0 1 100.00 66.66 33.33 133.33 00 0 1 0 100.00 66.66 33.33 200.00 00 0 1 1 100.00 66.66 33.33 166.66 00 1 0 0 n/an/an/an/a 00 1 0 1 100.00 66.66 33.33 100.00 00 1 1 0 100.00 66.66 33.33 400.00 00 1 1 1 100.00 66.66 33.33 200.00 01 0 0 0 100.00 66.66 33.33 100.00 01 0 0 1 100.00 66.66 33.33 133.33 01 0 1 0 100.00 66.66 33.33 200.00 01 0 1 1 100.00 66.66 33.33 166.66 01 1 0 0 100.00 66.66 33.33 100.00 01 1 0 1 100.00 66.66 33.33 133.33 01 1 1 0 100.00 66.66 33.33 200.00 01 1 1 1 100.00 66.66 33.33 166.66 1 0 0 0 0 100.00 66.66 33.33 266.66 10 0 0 1 100.00 66.66 33.33 133.33 10 0 1 0 100.00 66.66 33.33 200.00 10 0 1 1 100.00 66.66 33.33 166.66 10 1 0 0 n/a n/a n/a n/a 10 1 0 1 100.00 66.66 33.33 100.00 10 1 1 0 100.00 66.66 33.33 400.00 10 1 1 1 100.00 66.66 33.33 200.00 11 0 0 0 100.00 66.66 33.33 266.66 11 0 0 1 100.00 66.66 33.33 133.33 11 0 1 0 100.00 66.66 33.33 200.00 11 0 1 1 100.00 66.66 33.33 166.66 11 1 0 0 n/a n/a n/a n/a 11 1 0 1 100.00 66.66 33.33 100.00 11 1 1 0 100.00 66.66 33.33 400.00 11 1 1 1 100.00 66.66 33.33 200.00 vdda 1 56 gnd gnd 2 55 iref vddref 3 54 cpuclkt0 **fs l 0/ref0 4 53 cpuclkc0 fs l 1/ref1 5 52 gndcpu x1 6 51 cpuclkt1 x2 7 50 cpuclkc1 gndref 8 49 vddcpu vttpwr_gd/pd# 9 48 sdata vddpci 10 47 cpuclkt2_itp/pciext0 **fs l 2/pciclk0 11 46 cpuclkc2_itp/pciexc0 **fs3/~pciclk1 12 45 vddpciex pciclk2 13 44 pciext1 pciclk3 14 43 pciexc1 gndpci 15 42 pciext2 vddpci 16 41 pciexc2 pciclk4 17 40 gndpciex pciclk5 18 39 vddpciex gndpci 19 38 pciext3 *turbo# 20 37 pciexc3 reset# 21 36 pciext4 vdd48 22 35 pciexc4 **mode0/48mhz 23 34 pciext5/cpu_stop#* *sel24_48#/24_48mhz 24 33 pciexc5/pci_pciex_stop#* gnd48 25 32 gndpciex vdd3v66 26 31 sclk **itp_en/3v66_2 27 30 gnd3v66 **fs4/3v66_1 28 29 3v66_0 ~this output is default 2x drive strength. ics953002 56-pin ssop *these inputs have 120k internal pull-up resistors to vdd. **these inputs have 120k internal pull-down resistors to gnd.
2 integrated circuit systems, inc. ics953002 0924?11/18/09 pin description pin # pin name type description 1 vdda pwr 3.3v power for the pll core. 2 gnd pwr ground pin. 3 vddref pwr ref, xtal power supply, nominal 3.3v 4 **fsl0/ref0 i/o 3.3v tolerant input for cpu frequency selection. refer to input electrical characteristics for vil_fs and vih_fs values. / 14.318 mhz reference 5 fsl1/ref1 i/o 3.3v tolerant input for cpu frequency selection. refer to input electrical characteristics for vil_fs and vih_fs values. / 14.318 mhz reference 6 x1 in crystal input, nominally 14.318mhz. 7 x2 out crystal output, nominally 14.318mhz 8 gndref pwr ground pin for the ref outputs. 9 vttpwr_gd/pd# in this 3.3v lvttl input is a level sensitive strobe used to determine when latch inputs are valid and are ready to be sampled. this is an active high input. / asynchronous active low input pin used to power down the device into a low power s tate. 10 vddpci pwr power supply for pci clocks, nominal 3.3v 11 **fsl2/pciclk0 i/o 3.3v tolerant input for cpu frequency selection. refer to input electrical characteristics for vil_fs and vih_fs values. / 3.3v pci clock output. 12 **fs3/~pciclk1 i/o frequency select latch input pin / 3.3v pci clock output. 13 pciclk2 out pci clock output. 14 pciclk3 out pci clock output. 15 gndpci pwr ground pin for the pci outputs 16 vddpci pwr power supply for pci clocks, nominal 3.3v 17 pciclk4 out pci clock output. 18 pciclk5 out pci clock output. 19 gndpci pwr ground pin for the pci outputs 20 *turbo# in real time input pin to change frequency to a pre-programmed under or over clock entries located in the rom table. 21 reset# out real time system reset signal for frequency gear ratio change or watchdog timer timeout. this signal is active low. 22 vdd48 pwr power pin for the 48mhz output.3.3v 23 **mode0/48mhz i/o function select pin, 1=mobile mode, 0=desktop mode / 48mhz clock output. 3.3v. 24 *sel24_48#/24_48mhz i/o latched select input for 24/48mhz output / 24/48mhz clock output. 1=24mhz, 0 = 48mhz. 25 gnd48 pwr ground pin for the 48mhz outputs 26 vdd3v66 pwr power pin for the 3.3v 66mhz clocks. 27 **itp_en/3v66_2 i/o 3.3v 66.66mhz clock output./ itp_en: latched input to select pin functionality 1 = cpu_2_itp pair 0 = pci-ex0 pair 28 **fs4/3v66_1 i/o frequency select latch input pin / 66.66mhz clock output. 3.3v
3 integrated circuit systems, inc. ics953002 0924?11/18/09 pin description (continued) pin # pin name type description 29 3v66_0 out 3.3v 66.66mhz clock output 30 gnd3v66 pwr ground pin for the 3.3v 66mhz clocks 31 sclk in clock pin of smbus circuitry, 5v tolerant. 32 gndpciex pwr ground pin for the pci-ex outputs 33 pciexc5/pci_pciex_sto p#* out complement clock of differential pci_express pair. / active low signal that stops all pci and pciex clocks besides the free running clocks 34 pciext5/cpu_stop#* out true clock of differential pci_express pair./stops all cpuclk besides the free running clocks 35 pciexc4 out complement clock of differential pci_express pair. 36 pciext4 out true clock of differential pci_express pair. 37 pciexc3 out complement clock of differential pci_express pair. 38 pciext3 out true clock of differential pci_express pair. 39 vddpciex pwr power supply for pci express clocks, nominal 3.3v 40 gndpciex pwr ground pin for the pci-ex outputs 41 pciexc2 out complement clock of differential pci_express pair. 42 pciext2 out true clock of differential pci_express pair. 43 pciexc1 out complement clock of differential pci_express pair. 44 pciext1 out true clock of differential pci_express pair. 45 vddpciex pwr power supply for pci express clocks, nominal 3.3v 46 cpuclkc2_itp/pciexc0 out complementary clock of differential pair cpu outputs. these are current mode outputs. external resistors are required for voltage bias./ complement clock of differential pciex pair 47 cpuclkt2_itp/pciext0 out true clock of differential pair cpu outputs. these are current mode outputs. external resistors are required for voltage bias. / true clock of differential pciex pair 48 sdata i/o data pin for smbus circuitry, 5v tolerant. 49 vddcpu pwr supply for cpu clocks, 3.3v nominal 50 cpuclkc1 out complementary clock of differential pair cpu outputs. these are current mode outputs. external resistors are required for voltage bias. 51 cpuclkt1 out true clock of differential pair cpu outputs. these are current mode outputs. external resistors are required for voltage bias. 52 gndcpu pwr ground pin for the cpu outputs 53 cpuclkc0 out complementary clock of differential pair cpu outputs. these are current mode outputs. external resistors are required for voltage bias. 54 cpuclkt0 out true clock of differential pair cpu outputs. these are current mode outputs. external resistors are required for voltage bias. 55 iref out this pin establishes the reference current for the differential current-mode output pairs. this pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. 56 gnd pwr ground pin.
4 integrated circuit systems, inc. ics953002 0924?11/18/09 ics953002 is a 56-pin clock chip for p4 type processors with pci-express. the ics953002 is part of a whole new line of ics clock generators and buffers called tch? (timing control hub). this part incorporates ics's newest clock technology which offers more robust features and functionality. employing the use of a serially programmable i 2 c interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. m/n control can configure output frequency with resolution up to 0.1mhz increment. general description block diagram i ref reset# pll2 frequency dividers programmable spread pll1 programmable frequency dividers stop logic 48mhz 24_48mhz x1 x2 xtal sdata sclk vttpwrgd# pd# turbo# fs (4:0) sel24_48# mode0 control logic ref (1:0) cpuclkt (1:0) cpuclkc (1:0) cpuclkt2_itp/pciext0 cpuclkc2_itp/pciexc0 3v66 (2:0) pciclk (5:0) pci-ext (5:1) pci-exc (5:1)
5 integrated circuit systems, inc. ics953002 0924?11/18/09 table 1a. cpu pll1 turbo rom fs4 fs3 fsl2 fsl1 fsl0 cpufs4 cpufs3 cpufs2 cpufs1 cpufs0 cpu pci-ex agp pci spreadin g b0b4 b0b3 b0b2 b0b1 b0b0 b1bit4 b1bit3 b1bit2 b1bit1 b1bit0 mhz (default) (default) (default) % 0000 0 00000 n/a n/a n/a n/a down sp 0-0.5 % 0000 0 00001 n/a n/a n/a n/a center +/- 0.25 0000 0 00010 n/a n/a n/a n/a center +/- 0.25 0000 0 00011 n/a n/a n/a n/a center +/- 0.25 0000 0 00100n/an/an/an/a center +/- 0.25 0000 0 00101 n/a n/a n/a n/a center +/- 0.25 0000 0 00110 n/a n/a n/a n/a center +/- 0.25 0000 0 00111 n/a n/a n/a n/a center +/- 0.25 0000 0 01000 266.67 100.00 66.67 33.33 down s p 0-0.5 % 0000 0 01001 269.33 101.00 67.33 33.67 center +/- 0.25 0000 0 01010 274.67 103.00 68.67 34.33 center +/- 0.25 0000 0 01011 280.00 105.00 70.00 35.00 center +/- 0.25 0000 0 01100 285.33 107.00 71.33 35.67 center +/- 0.25 0000 0 01101 290.67 109.00 72.67 36.33 center +/- 0.25 0000 0 01110 293.33 110.00 73.33 36.67 center +/- 0.25 0000 0 01111 296.00 111.00 74.00 37.00 center +/- 0.25 0000 0 10000222.22111.1166.6733.33 down sp 0-0.5 % 0000 0 10001 224.44 112.22 67.33 33.67 center +/- 0.25 0000 0 10010 228.89 114.44 68.67 34.33 center +/- 0.25 0000 0 10011 233.33 116.67 70.00 35.00 center +/- 0.25 0000 0 10100 237.78 118.89 71.33 35.67 center +/- 0.25 0000 0 10101 242.22 121.11 72.67 36.33 center +/- 0.25 0000 0 10110 244.44 122.22 73.33 36.67 center +/- 0.25 0000 0 10111 246.66 123.33 74.00 37.00 center +/- 0.25 0000 0 11000 266.67 100.00 66.67 33.33 down sp 0-0.5 % 0000 0 11001 269.33 101.00 67.33 33.67 center +/- 0.25 0000 0 11010 274.67 103.00 68.67 34.33 center +/- 0.25 0000 0 11011 280.00 105.00 70.00 35.00 center +/- 0.25 0000 0 11100 285.33 107.00 71.33 35.67 center +/- 0.25 0000 0 11101 290.67 109.00 72.67 36.33 center +/- 0.25 0000 0 11110 293.33 110.00 73.33 36.67 center +/- 0.25 0000 0 11111 296.00 111.00 74.00 37.00 center +/- 0.25
6 integrated circuit systems, inc. ics953002 0924?11/18/09 table 1a. cpu pll1 turbo rom (continued) fs4 fs3 fsl2 fsl1 fsl0 cpufs4 cpufs3 cpufs2 cpufs1 cpufs0 cpu pci-ex agp pci spreadin g b0b4 b0b3 b0b2 b0b1 b0b0 b1bit4 b1bit3 b1bit2 b1bit1 b1bit0 mhz (default) (default) (default) % 0000 1 00000 n/a n/a n/a n/a down sp 0-0.5 % 0000 1 00001 n/a n/a n/a n/a center +/- 0.25 0000 1 00010 n/a n/a n/a n/a center +/- 0.25 0000 1 00011 n/a n/a n/a n/a center +/- 0.25 0000 1 00100 n/a n/a n/a n/a center +/- 0.25 0000 1 00101 n/a n/a n/a n/a center +/- 0.25 0000 1 00110 n/a n/a n/a n/a center +/- 0.25 0000 1 00111 n/a n/a n/a n/a center +/- 0.25 0000 1 01000 133.33 100.00 66.67 33.33 down s p 0-0.5 % 0000 1 01001 134.67 101.00 67.33 33.67 center +/- 0.25 0000 1 01010 137.33 103.00 68.67 34.33 center +/- 0.25 0000 1 01011 140.00 105.00 70.00 35.00 center +/- 0.25 0000 1 01100 142.67 107.00 71.33 35.67 center +/- 0.25 0000 1 01101 145.33 109.00 72.67 36.33 center +/- 0.25 0000 1 01110 146.67 110.00 73.33 36.67 center +/- 0.25 0000 1 01111 148.00 111.00 74.00 37.00 center +/- 0.25 0000 1 10000 111.11 111.11 66.67 33.33 down sp 0-0.5 % 0000 1 10001 112.22 112.22 67.33 33.67 center +/- 0.25 0000 1 10010 114.44 114.44 68.67 34.33 center +/- 0.25 0000 1 10011 116.67 116.67 70.00 35.00 center +/- 0.25 0000 1 10100 118.89 118.89 71.33 35.67 center +/- 0.25 0000 1 10101 121.11 121.11 72.67 36.33 center +/- 0.25 0000 1 10110 122.22 122.22 73.33 36.67 center +/- 0.25 0000 1 10111 123.33 123.33 74.00 37.00 center +/- 0.25 0000 1 11000 133.33 100.00 66.67 33.33 down sp 0-0.5 % 0000 1 11001 134.67 101.00 67.33 33.67 center +/- 0.25 0000 1 11010 137.33 103.00 68.67 34.33 center +/- 0.25 0000 1 11011 140.00 105.00 70.00 35.00 center +/- 0.25 0000 1 11100 142.67 107.00 71.33 35.67 center +/- 0.25 0000 1 11101 145.33 109.00 72.67 36.33 center +/- 0.25 0000 1 11110 146.67 110.00 73.33 36.67 center +/- 0.25 0000 1 11111 148.00 111.00 74.00 37.00 center +/- 0.25
7 integrated circuit systems, inc. ics953002 0924?11/18/09 table 1a. cpu pll1 turbo rom (continued) fs4 fs3 fsl2 fsl1 fsl0 cpufs4 cpufs3 cpufs2 cpufs1 cpufs0 cpu pci-ex agp pci spreadin g b0b4 b0b3 b0b2 b0b1 b0b0 b1bit4 b1bit3 b1bit2 b1bit1 b1bit0 mhz (default) (default) (default) % 0001 0 00000 n/a n/a n/a n/a down sp 0-0.5 % 0001 0 00001 n/a n/a n/a n/a center +/- 0.25 0001 0 00010 n/a n/a n/a n/a center +/- 0.25 0001 0 00011 n/a n/a n/a n/a center +/- 0.25 0001 0 00100 n/a n/a n/a n/a center +/- 0.25 0001 0 00101 n/a n/a n/a n/a center +/- 0.25 0001 0 00110 n/a n/a n/a n/a center +/- 0.25 0001 0 00111 n/a n/a n/a n/a center +/- 0.25 0001 0 01000 200.00 100.00 66.67 33.33 down s p 0-0.5 % 0001 0 01001 202.00 101.00 67.33 33.67 center +/- 0.25 0001 0 01010 206.00 103.00 68.67 34.33 center +/- 0.25 0001 0 01011 210.00 105.00 70.00 35.00 center +/- 0.25 0001 0 01100 214.00 107.00 71.33 35.67 center +/- 0.25 0001 0 01101 218.00 109.00 72.67 36.33 center +/- 0.25 0001 0 01110 220.00 110.00 73.33 36.67 center +/- 0.25 0001 0 01111 222.00 111.00 74.00 37.00 center +/- 0.25 0001 0 10000 166.67 111.11 66.67 33.33 down sp 0-0.5 % 0001 0 10001 168.33 112.22 67.33 33.67 center +/- 0.25 0001 0 10010 171.66 114.44 68.67 34.33 center +/- 0.25 0001 0 10011 175.00 116.67 70.00 35.00 center +/- 0.25 0001 0 10100 178.33 118.89 71.33 35.67 center +/- 0.25 0001 0 10101 181.66 121.11 72.67 36.33 center +/- 0.25 0001 0 10110 183.33 122.22 73.33 36.67 center +/- 0.25 0001 0 10111 185.00 123.33 74.00 37.00 center +/- 0.25 0001 0 11000 200.00 100.00 66.67 33.33 down sp 0-0.5 % 0001 0 11001 202.00 101.00 67.33 33.67 center +/- 0.25 0001 0 11010 206.00 103.00 68.67 34.33 center +/- 0.25 0001 0 11011 210.00 105.00 70.00 35.00 center +/- 0.25 0001 0 11100 214.00 107.00 71.33 35.67 center +/- 0.25 0001 0 11101 218.00 109.00 72.67 36.33 center +/- 0.25 0001 0 11110 220.00 110.00 73.33 36.67 center +/- 0.25 0001 0 11111 222.00 111.00 74.00 37.00 center +/- 0.25
8 integrated circuit systems, inc. ics953002 0924?11/18/09 table 1a. cpu pll1 turbo rom (continued) fs4 fs3 fsl2 fsl1 fsl0 cpufs4 cpufs3 cpufs2 cpufs1 cpufs0 cpu pci-ex agp pci spreadin g b0b4 b0b3 b0b2 b0b1 b0b0 b1bit4 b1bit3 b1bit2 b1bit1 b1bit0 mhz (default) (default) (default) % 0001 1 00000 n/a n/a n/a n/a down sp 0-0.5 % 0001 1 00001 n/a n/a n/a n/a center +/- 0.25 0001 1 00010 n/a n/a n/a n/a center +/- 0.25 0001 1 00011 n/a n/a n/a n/a center +/- 0.25 0001 1 00100 n/a n/a n/a n/a center +/- 0.25 0001 1 00101 n/a n/a n/a n/a center +/- 0.25 0001 1 00110 n/a n/a n/a n/a center +/- 0.25 0001 1 00111 n/a n/a n/a n/a center +/- 0.25 0001 1 01000 200.00 100.00 66.67 33.33 down s p 0-0.5 % 0001 1 01001 202.00 101.00 67.33 33.67 center +/- 0.25 0001 1 01010 206.00 103.00 68.67 34.33 center +/- 0.25 0001 1 01011 210.00 105.00 70.00 35.00 center +/- 0.25 0001 1 01100 214.00 107.00 71.33 35.67 center +/- 0.25 0001 1 01101 218.00 109.00 72.67 36.33 center +/- 0.25 0001 1 01110 220.00 110.00 73.33 36.67 center +/- 0.25 0001 1 01111 222.00 111.00 74.00 37.00 center +/- 0.25 0001 1 10000 166.67 111.11 66.67 33.33 down sp 0-0.5 % 0001 1 10001 168.33 112.22 67.33 33.67 center +/- 0.25 0001 1 10010 171.66 114.44 68.67 34.33 center +/- 0.25 0001 1 10011 175.00 116.67 70.00 35.00 center +/- 0.25 0001 1 10100 178.33 118.89 71.33 35.67 center +/- 0.25 0001 1 10101 181.66 121.11 72.67 36.33 center +/- 0.25 0001 1 10110 183.33 122.22 73.33 36.67 center +/- 0.25 0001 1 10111 185.00 123.33 74.00 37.00 center +/- 0.25 0001 1 11000 200.00 100.00 66.67 33.33 down sp 0-0.5 % 0001 1 11001 202.00 101.00 67.33 33.67 center +/- 0.25 0001 1 11010 206.00 103.00 68.67 34.33 center +/- 0.25 0001 1 11011 210.00 105.00 70.00 35.00 center +/- 0.25 0001 1 11100 214.00 107.00 71.33 35.67 center +/- 0.25 0001 1 11101 218.00 109.00 72.67 36.33 center +/- 0.25 0001 1 11110 220.00 110.00 73.33 36.67 center +/- 0.25 0001 1 11111 222.00 111.00 74.00 37.00 center +/- 0.25
9 integrated circuit systems, inc. ics953002 0924?11/18/09 table 1a. cpu pll1 turbo rom (continued) fs4 fs3 fsl2 fsl1 fsl0 cpufs4 cpufs3 cpufs2 cpufs1 cpufs0 cpu pci-ex agp pci spreading b0b4 b0b3 b0b2 b0b1 b0b0 b1bit4 b1bit3 b1bit2 b1bit1 b1bit0 mhz (default) (default) (default) % 0010 0 00000 n/a n/a n/a n/a down sp 0-0.5 % 0010 0 00001 n/a n/a n/a n/a center +/- 0.25 0010 0 00010 n/a n/a n/a n/a center +/- 0.25 0010 0 00011 n/a n/a n/a n/a center +/- 0.25 0010 0 00100n/an/an/an/a center +/- 0.25 0010 0 00101 n/a n/a n/a n/a center +/- 0.25 0010 0 00110 n/a n/a n/a n/a center +/- 0.25 0010 0 00111 n/a n/a n/a n/a center +/- 0.25 0010 0 01000 266.67 100.00 66.67 33.33 down sp 0-0.5 % 0010 0 01001 269.33 101.00 67.33 33.67 center +/- 0.25 0010 0 01010 274.67 103.00 68.67 34.33 center +/- 0.25 0010 0 01011 280.00 105.00 70.00 35.00 center +/- 0.25 0010 0 01100 285.33 107.00 71.33 35.67 center +/- 0.25 0010 0 01101 290.67 109.00 72.67 36.33 center +/- 0.25 0010 0 01110 293.33 110.00 73.33 36.67 center +/- 0.25 0010 0 01111 296.00 111.00 74.00 37.00 center +/- 0.25 0010 0 10000222.22111.1166.6733.33 down sp 0-0.5 % 0010 0 10001 224.44 112.22 67.33 33.67 center +/- 0.25 0010 0 10010 228.89 114.44 68.67 34.33 center +/- 0.25 0010 0 10011 233.33 116.67 70.00 35.00 center +/- 0.25 0010 0 10100 237.78 118.89 71.33 35.67 center +/- 0.25 0010 0 10101 242.22 121.11 72.67 36.33 center +/- 0.25 0010 0 10110 244.44 122.22 73.33 36.67 center +/- 0.25 0010 0 10111 246.66 123.33 74.00 37.00 center +/- 0.25 0010 0 11000 266.67 100.00 66.67 33.33 down sp 0-0.5 % 0010 0 11001 269.33 101.00 67.33 33.67 center +/- 0.25 0010 0 11010 274.67 103.00 68.67 34.33 center +/- 0.25 0010 0 11011 280.00 105.00 70.00 35.00 center +/- 0.25 0010 0 11100 285.33 107.00 71.33 35.67 center +/- 0.25 0010 0 11101 290.67 109.00 72.67 36.33 center +/- 0.25 0010 0 11110 293.33 110.00 73.33 36.67 center +/- 0.25 0010 0 11111 296.00 111.00 74.00 37.00 center +/- 0.25
10 integrated circuit systems, inc. ics953002 0924?11/18/09 table 1a. cpu pll1 turbo rom (continued) fs4 fs3 fsl2 fsl1 fsl0 cpufs4 cpufs3 cpufs2 cpufs1 cpufs0 cpu pci-ex agp pci spreadin g b0b4 b0b3 b0b2 b0b1 b0b0 b1bit4 b1bit3 b1bit2 b1bit1 b1bit0 mhz (default) (default) (default) % 0010 1 00000 n/a n/a n/a n/a down s p 0-0.5 % 0010 1 00001 n/a n/a n/a n/a center +/- 0.25 0010 1 00010 n/a n/a n/a n/a center +/- 0.25 0010 1 00011 n/a n/a n/a n/a center +/- 0.25 0010 1 00100 n/a n/a n/a n/a center +/- 0.25 0010 1 00101 n/a n/a n/a n/a center +/- 0.25 0010 1 00110 n/a n/a n/a n/a center +/- 0.25 0010 1 00111 n/a n/a n/a n/a center +/- 0.25 0010 1 01000 100.00 100.00 66.67 33.33 down s p 0-0.5 % 0010 1 01001 101.00 101.00 67.33 33.67 center +/- 0.25 0010 1 01010 103.00 103.00 68.67 34.33 center +/- 0.25 0010 1 01011 105.00 105.00 70.00 35.00 center +/- 0.25 0010 1 01100 107.00 107.00 71.33 35.67 center +/- 0.25 0010 1 01101 109.00 109.00 72.67 36.33 center +/- 0.25 0010 1 01110 110.00 110.00 73.33 36.67 center +/- 0.25 0010 1 01111 111.00 111.00 74.00 37.00 center +/- 0.25 0010 1 10000 83.33 111.11 66.67 33.33 down sp 0-0.5 % 0010 1 10001 84.17 112.22 67.33 33.67 center +/- 0.25 0010 1 10010 85.83 114.44 68.67 34.33 center +/- 0.25 0010 1 10011 87.50 116.67 70.00 35.00 center +/- 0.25 0010 1 10100 89.17 118.89 71.33 35.67 center +/- 0.25 0010 1 10101 90.83 121.11 72.67 36.33 center +/- 0.25 0010 1 10110 91.67 122.22 73.33 36.67 center +/- 0.25 0010 1 10111 92.50 123.33 74.00 37.00 center +/- 0.25 0010 1 11000 100.00 100.00 66.67 33.33 down sp 0-0.5 % 0010 1 11001 101.00 101.00 67.33 33.67 center +/- 0.25 0010 1 11010 103.00 103.00 68.67 34.33 center +/- 0.25 0010 1 11011 105.00 105.00 70.00 35.00 center +/- 0.25 0010 1 11100 107.00 107.00 71.33 35.67 center +/- 0.25 0010 1 11101 109.00 109.00 72.67 36.33 center +/- 0.25 0010 1 11110 110.00 110.00 73.33 36.67 center +/- 0.25 0010 1 11111 111.00 111.00 74.00 37.00 center +/- 0.25
11 integrated circuit systems, inc. ics953002 0924?11/18/09 table 1a. cpu pll1 turbo rom (continued) fs4 fs3 fsl2 fsl1 fsl0 cpufs4 cpufs3 cpufs2 cpufs1 cpufs0 cpu pci-ex agp pci spreading b0b4 b0b3 b0b2 b0b1 b0b0 b1bit4 b1bit3 b1bit2 b1bit1 b1bit0 mhz (default) (default) (default) % 0011 0 00000 n/a n/a n/a n/a down s p 0-0.5 % 0011 0 00001 n/a n/a n/a n/a center +/- 0.25 0011 0 00010 n/a n/a n/a n/a center +/- 0.25 0011 0 00011 n/a n/a n/a n/a center +/- 0.25 0011 0 00100 n/a n/a n/a n/a center +/- 0.25 0011 0 00101 n/a n/a n/a n/a center +/- 0.25 0011 0 00110 n/a n/a n/a n/a center +/- 0.25 0011 0 00111 n/a n/a n/a n/a center +/- 0.25 0011 0 01000 400.00 100.00 66.67 33.33 down s p 0-0.5 % 0011 0 01001 404.00 101.00 67.33 33.67 center +/- 0.25 0011 0 01010 412.00 103.00 68.67 34.33 center +/- 0.25 0011 0 01011 420.00 105.00 70.00 35.00 center +/- 0.25 0011 0 01100 428.00 107.00 71.33 35.67 center +/- 0.25 0011 0 01101 436.00 109.00 72.67 36.33 center +/- 0.25 0011 0 01110 440.00 110.00 73.33 36.67 center +/- 0.25 0011 0 01111 444.00 111.00 74.00 37.00 center +/- 0.25 0011 0 10000 333.33 111.11 66.67 33.33 down sp 0-0.5 % 0011 0 10001 336.66 112.22 67.33 33.67 center +/- 0.25 0011 0 10010 343.33 114.44 68.67 34.33 center +/- 0.25 0011 0 10011 350.00 116.67 70.00 35.00 center +/- 0.25 0011 0 10100 356.66 118.89 71.33 35.67 center +/- 0.25 0011 0 10101 363.33 121.11 72.67 36.33 center +/- 0.25 0011 0 10110 366.66 122.22 73.33 36.67 center +/- 0.25 0011 0 10111 370.00 123.33 74.00 37.00 center +/- 0.25 0011 0 11000 400.00 100.00 66.67 33.33 down sp 0-0.5 % 0011 0 11001 404.00 101.00 67.33 33.67 center +/- 0.25 0011 0 11010 412.00 103.00 68.67 34.33 center +/- 0.25 0011 0 11011 420.00 105.00 70.00 35.00 center +/- 0.25 0011 0 11100 428.00 107.00 71.33 35.67 center +/- 0.25 0011 0 11101 436.00 109.00 72.67 36.33 center +/- 0.25 0011 0 11110 440.00 110.00 73.33 36.67 center +/- 0.25 0011 0 11111 444.00 111.00 74.00 37.00 center +/- 0.25
12 integrated circuit systems, inc. ics953002 0924?11/18/09 table 1a. cpu pll1 turbo rom (continued) fs4 fs3 fsl2 fsl1 fsl0 cpufs4 cpufs3 cpufs2 cpufs1 cpufs0 cpu pci-ex agp pci spreading b0b4 b0b3 b0b2 b0b1 b0b0 b1bit4 b1bit3 b1bit2 b1bit1 b1bit0 mhz (default) (default) (default) % 0011 1 00000 n/a n/a n/a n/a down s p 0-0.5 % 0011 1 00001 n/a n/a n/a n/a center +/- 0.25 0011 1 00010 n/a n/a n/a n/a center +/- 0.25 0011 1 00011 n/a n/a n/a n/a center +/- 0.25 0011 1 00100 n/a n/a n/a n/a center +/- 0.25 0011 1 00101 n/a n/a n/a n/a center +/- 0.25 0011 1 00110 n/a n/a n/a n/a center +/- 0.25 0011 1 00111 n/a n/a n/a n/a center +/- 0.25 0011 1 01000 200.00 100.00 66.67 33.33 down s p 0-0.5 % 0011 1 01001 202.00 101.00 67.33 33.67 center +/- 0.25 0011 1 01010 206.00 103.00 68.67 34.33 center +/- 0.25 0011 1 01011 210.00 105.00 70.00 35.00 center +/- 0.25 0011 1 01100 214.00 107.00 71.33 35.67 center +/- 0.25 0011 1 01101 218.00 109.00 72.67 36.33 center +/- 0.25 0011 1 01110 220.00 110.00 73.33 36.67 center +/- 0.25 0011 1 01111 222.00 111.00 74.00 37.00 center +/- 0.25 0011 1 10000 166.67 111.11 66.67 33.33 down sp 0-0.5 % 0011 1 10001 168.33 112.22 67.33 33.67 center +/- 0.25 0011 1 10010 171.66 114.44 68.67 34.33 center +/- 0.25 0011 1 10011 175.00 116.67 70.00 35.00 center +/- 0.25 0011 1 10100 178.33 118.89 71.33 35.67 center +/- 0.25 0011 1 10101 181.66 121.11 72.67 36.33 center +/- 0.25 0011 1 10110 183.33 122.22 73.33 36.67 center +/- 0.25 0011 1 10111 185.00 123.33 74.00 37.00 center +/- 0.25 0011 1 11000 200.00 100.00 66.67 33.33 down sp 0-0.5 % 0011 1 11001 202.00 101.00 67.33 33.67 center +/- 0.25 0011 1 11010 206.00 103.00 68.67 34.33 center +/- 0.25 0011 1 11011 210.00 105.00 70.00 35.00 center +/- 0.25 0011 1 11100 214.00 107.00 71.33 35.67 center +/- 0.25 0011 1 11101 218.00 109.00 72.67 36.33 center +/- 0.25 0011 1 11110 220.00 110.00 73.33 36.67 center +/- 0.25 0011 1 11111 222.00 111.00 74.00 37.00 center +/- 0.25
13 integrated circuit systems, inc. ics953002 0924?11/18/09 table 1a. cpu pll1 turbo rom (continued) fs4 fs3 fsl2 fsl1 fsl0 cpufs4 cpufs3 cpufs2 cpufs1 cpufs0 cpu pci-ex agp pci spreadin g b0b4 b0b3 b0b2 b0b1 b0b0 b1bit4 b1bit3 b1bit2 b1bit1 b1bit0 mhz (default) (default) (default) % 0100 0 00000 n/a n/a n/a n/a down sp 0-0.5 % 0100 0 00001 n/a n/a n/a n/a center +/- 0.25 0100 0 00010 n/a n/a n/a n/a center +/- 0.25 0100 0 00011 n/a n/a n/a n/a center +/- 0.25 0100 0 0 0 1 0 0 n/a n/a n/a n/a center +/- 0.25 0100 0 00101 n/a n/a n/a n/a center +/- 0.25 0100 0 00110 n/a n/a n/a n/a center +/- 0.25 0100 0 00111 n/a n/a n/a n/a center +/- 0.25 0100 0 01000 100.00 100.00 66.67 33.33 down s p 0-0.5 % 0100 0 01001 101.00 101.00 67.33 33.67 center +/- 0.25 0100 0 01010 103.00 103.00 68.67 34.33 center +/- 0.25 0100 0 01011 105.00 105.00 70.00 35.00 center +/- 0.25 0100 0 01100 107.00 107.00 71.33 35.67 center +/- 0.25 0100 0 01101 109.00 109.00 72.67 36.33 center +/- 0.25 0100 0 01110 110.00 110.00 73.33 36.67 center +/- 0.25 0100 0 01111 111.00 111.00 74.00 37.00 center +/- 0.25 0100 0 1 0 0 0 0 83.33 111.11 66.67 33.33 down sp 0-0.5 % 0100 0 10001 84.17 112.22 67.33 33.67 center +/- 0.25 0100 0 10010 85.83 114.44 68.67 34.33 center +/- 0.25 0100 0 10011 87.50 116.67 70.00 35.00 center +/- 0.25 0100 0 10100 89.17 118.89 71.33 35.67 center +/- 0.25 0100 0 10101 90.83 121.11 72.67 36.33 center +/- 0.25 0100 0 10110 91.67 122.22 73.33 36.67 center +/- 0.25 0100 0 10111 92.50 123.33 74.00 37.00 center +/- 0.25 0100 0 11000 100.00 100.00 66.67 33.33 down sp 0-0.5 % 0100 0 11001 101.00 101.00 67.33 33.67 center +/- 0.25 0100 0 11010 103.00 103.00 68.67 34.33 center +/- 0.25 0100 0 11011 105.00 105.00 70.00 35.00 center +/- 0.25 0100 0 11100 107.00 107.00 71.33 35.67 center +/- 0.25 0100 0 11101 109.00 109.00 72.67 36.33 center +/- 0.25 0100 0 11110 110.00 110.00 73.33 36.67 center +/- 0.25 0100 0 11111 111.00 111.00 74.00 37.00 center +/- 0.25
14 integrated circuit systems, inc. ics953002 0924?11/18/09 table 1a. cpu pll1 turbo rom (continued) fs4 fs3 fsl2 fsl1 fsl0 cpufs4 cpufs3 cpufs2 cpufs1 cpufs0 cpu pci-ex agp pci spreading b0b4 b0b3 b0b2 b0b1 b0b0 b1bit4 b1bit3 b1bit2 b1bit1 b1bit0 mhz (default) (default) (default) % 0100 1 00000 n/a n/a n/a n/a down s p 0-0.5 % 0100 1 00001 n/a n/a n/a n/a center +/- 0.25 0100 1 00010 n/a n/a n/a n/a center +/- 0.25 0100 1 00011 n/a n/a n/a n/a center +/- 0.25 0100 1 00100 n/a n/a n/a n/a center +/- 0.25 0100 1 00101 n/a n/a n/a n/a center +/- 0.25 0100 1 00110 n/a n/a n/a n/a center +/- 0.25 0100 1 00111 n/a n/a n/a n/a center +/- 0.25 0100 1 01000 133.33 100.00 66.67 33.33 down s p 0-0.5 % 0100 1 01001 134.67 101.00 67.33 33.67 center +/- 0.25 0100 1 01010 137.33 103.00 68.67 34.33 center +/- 0.25 0100 1 01011 140.00 105.00 70.00 35.00 center +/- 0.25 0100 1 01100 142.67 107.00 71.33 35.67 center +/- 0.25 0100 1 01101 145.33 109.00 72.67 36.33 center +/- 0.25 0100 1 01110 146.67 110.00 73.33 36.67 center +/- 0.25 0100 1 01111 148.00 111.00 74.00 37.00 center +/- 0.25 0100 1 10000 111.11 111.11 66.67 33.33 down sp 0-0.5 % 0100 1 10001 112.22 112.22 67.33 33.67 center +/- 0.25 0100 1 10010 114.44 114.44 68.67 34.33 center +/- 0.25 0100 1 10011 116.67 116.67 70.00 35.00 center +/- 0.25 0100 1 10100 118.89 118.89 71.33 35.67 center +/- 0.25 0100 1 10101 121.11 121.11 72.67 36.33 center +/- 0.25 0100 1 10110 122.22 122.22 73.33 36.67 center +/- 0.25 0100 1 10111 123.33 123.33 74.00 37.00 center +/- 0.25 0100 1 11000 133.33 100.00 66.67 33.33 down sp 0-0.5 % 0100 1 11001 134.67 101.00 67.33 33.67 center +/- 0.25 0100 1 11010 137.33 103.00 68.67 34.33 center +/- 0.25 0100 1 11011 140.00 105.00 70.00 35.00 center +/- 0.25 0100 1 11100 142.67 107.00 71.33 35.67 center +/- 0.25 0100 1 11101 145.33 109.00 72.67 36.33 center +/- 0.25 0100 1 11110 146.67 110.00 73.33 36.67 center +/- 0.25 0100 1 11111 148.00 111.00 74.00 37.00 center +/- 0.25
15 integrated circuit systems, inc. ics953002 0924?11/18/09 table 1a. cpu pll1 turbo rom (continued) fs4 fs3 fsl2 fsl1 fsl0 cpufs4 cpufs3 cpufs2 cpufs1 cpufs0 cpu pci-ex agp pci spreading b0b4 b0b3 b0b2 b0b1 b0b0 b1bit4 b1bit3 b1bit2 b1bit1 b1bit0 mhz (default) (default) (default) % 0101 0 00000 n/a n/a n/a n/a down s p 0-0.5 % 0101 0 00001 n/a n/a n/a n/a center +/- 0.25 0101 0 00010 n/a n/a n/a n/a center +/- 0.25 0101 0 00011 n/a n/a n/a n/a center +/- 0.25 0101 0 00100 n/a n/a n/a n/a center +/- 0.25 0101 0 00101 n/a n/a n/a n/a center +/- 0.25 0101 0 00110 n/a n/a n/a n/a center +/- 0.25 0101 0 00111 n/a n/a n/a n/a center +/- 0.25 0101 0 01000 200.00 100.00 66.67 33.33 down s p 0-0.5 % 0101 0 01001 202.00 101.00 67.33 33.67 center +/- 0.25 0101 0 01010 206.00 103.00 68.67 34.33 center +/- 0.25 0101 0 01011 210.00 105.00 70.00 35.00 center +/- 0.25 0101 0 01100 214.00 107.00 71.33 35.67 center +/- 0.25 0101 0 01101 218.00 109.00 72.67 36.33 center +/- 0.25 0101 0 01110 220.00 110.00 73.33 36.67 center +/- 0.25 0101 0 01111 222.00 111.00 74.00 37.00 center +/- 0.25 0101 0 10000 166.67 111.11 66.67 33.33 down sp 0-0.5 % 0101 0 10001 168.33 112.22 67.33 33.67 center +/- 0.25 0101 0 10010 171.66 114.44 68.67 34.33 center +/- 0.25 0101 0 10011 175.00 116.67 70.00 35.00 center +/- 0.25 0101 0 10100 178.33 118.89 71.33 35.67 center +/- 0.25 0101 0 10101 181.66 121.11 72.67 36.33 center +/- 0.25 0101 0 10110 183.33 122.22 73.33 36.67 center +/- 0.25 0101 0 10111 185.00 123.33 74.00 37.00 center +/- 0.25 0101 0 11000 200.00 100.00 66.67 33.33 down sp 0-0.5 % 0101 0 11001 202.00 101.00 67.33 33.67 center +/- 0.25 0101 0 11010 206.00 103.00 68.67 34.33 center +/- 0.25 0101 0 11011 210.00 105.00 70.00 35.00 center +/- 0.25 0101 0 11100 214.00 107.00 71.33 35.67 center +/- 0.25 0101 0 11101 218.00 109.00 72.67 36.33 center +/- 0.25 0101 0 11110 220.00 110.00 73.33 36.67 center +/- 0.25 0101 0 11111 222.00 111.00 74.00 37.00 center +/- 0.25
16 integrated circuit systems, inc. ics953002 0924?11/18/09 table 1a. cpu pll1 turbo rom (continued) fs4 fs3 fsl2 fsl1 fsl0 cpufs4 cpufs3 cpufs2 cpufs1 cpufs0 cpu pci-ex agp pci spreading b0b4 b0b3 b0b2 b0b1 b0b0 b1bit4 b1bit3 b1bit2 b1bit1 b1bit0 mhz (default) (default) (default) % 0101 1 00000 n/a n/a n/a n/a down s p 0-0.5 % 0101 1 00001 n/a n/a n/a n/a center +/- 0.25 0101 1 00010 n/a n/a n/a n/a center +/- 0.25 0101 1 00011 n/a n/a n/a n/a center +/- 0.25 0101 1 00100 n/a n/a n/a n/a center +/- 0.25 0101 1 00101 n/a n/a n/a n/a center +/- 0.25 0101 1 00110 n/a n/a n/a n/a center +/- 0.25 0101 1 00111 n/a n/a n/a n/a center +/- 0.25 0101 1 01000 200.00 100.00 66.67 33.33 down s p 0-0.5 % 0101 1 01001 202.00 101.00 67.33 33.67 center +/- 0.25 0101 1 01010 206.00 103.00 68.67 34.33 center +/- 0.25 0101 1 01011 210.00 105.00 70.00 35.00 center +/- 0.25 0101 1 01100 214.00 107.00 71.33 35.67 center +/- 0.25 0101 1 01101 218.00 109.00 72.67 36.33 center +/- 0.25 0101 1 01110 220.00 110.00 73.33 36.67 center +/- 0.25 0101 1 01111 222.00 111.00 74.00 37.00 center +/- 0.25 0101 1 10000 166.67 111.11 66.67 33.33 down sp 0-0.5 % 0101 1 10001 168.33 112.22 67.33 33.67 center +/- 0.25 0101 1 10010 171.66 114.44 68.67 34.33 center +/- 0.25 0101 1 10011 175.00 116.67 70.00 35.00 center +/- 0.25 0101 1 10100 178.33 118.89 71.33 35.67 center +/- 0.25 0101 1 10101 181.66 121.11 72.67 36.33 center +/- 0.25 0101 1 10110 183.33 122.22 73.33 36.67 center +/- 0.25 0101 1 10111 185.00 123.33 74.00 37.00 center +/- 0.25 0101 1 11000 200.00 100.00 66.67 33.33 down sp 0-0.5 % 0101 1 11001 202.00 101.00 67.33 33.67 center +/- 0.25 0101 1 11010 206.00 103.00 68.67 34.33 center +/- 0.25 0101 1 11011 210.00 105.00 70.00 35.00 center +/- 0.25 0101 1 11100 214.00 107.00 71.33 35.67 center +/- 0.25 0101 1 11101 218.00 109.00 72.67 36.33 center +/- 0.25 0101 1 11110 220.00 110.00 73.33 36.67 center +/- 0.25 0101 1 11111 222.00 111.00 74.00 37.00 center +/- 0.25
17 integrated circuit systems, inc. ics953002 0924?11/18/09 table 1a. cpu pll1 turbo rom (continued) fs4 fs3 fsl2 fsl1 fsl0 cpufs4 cpufs3 cpufs2 cpufs1 cpufs0 cpu pci-ex agp pci spreadin g b0b4 b0b3 b0b2 b0b1 b0b0 b1bit4 b1bit3 b1bit2 b1bit1 b1bit0 mhz (default) (default) (default) % 0110 0 00000 n/a n/a n/a n/a down sp 0-0.5 % 0110 0 00001 n/a n/a n/a n/a center +/- 0.25 0110 0 00010 n/a n/a n/a n/a center +/- 0.25 0110 0 00011 n/a n/a n/a n/a center +/- 0.25 0110 0 0 0 1 0 0 n/a n/a n/a n/a center +/- 0.25 0110 0 00101 n/a n/a n/a n/a center +/- 0.25 0110 0 00110 n/a n/a n/a n/a center +/- 0.25 0110 0 00111 n/a n/a n/a n/a center +/- 0.25 0110 0 01000 100.00 100.00 66.67 33.33 down s p 0-0.5 % 0110 0 01001 101.00 101.00 67.33 33.67 center +/- 0.25 0110 0 01010 103.00 103.00 68.67 34.33 center +/- 0.25 0110 0 01011 105.00 105.00 70.00 35.00 center +/- 0.25 0110 0 01100 107.00 107.00 71.33 35.67 center +/- 0.25 0110 0 01101 109.00 109.00 72.67 36.33 center +/- 0.25 0110 0 01110 110.00 110.00 73.33 36.67 center +/- 0.25 0110 0 01111 111.00 111.00 74.00 37.00 center +/- 0.25 0110 0 1 0 0 0 0 83.33 111.11 66.67 33.33 down sp 0-0.5 % 0110 0 10001 84.17 112.22 67.33 33.67 center +/- 0.25 0110 0 10010 85.83 114.44 68.67 34.33 center +/- 0.25 0110 0 10011 87.50 116.67 70.00 35.00 center +/- 0.25 0110 0 10100 89.17 118.89 71.33 35.67 center +/- 0.25 0110 0 10101 90.83 121.11 72.67 36.33 center +/- 0.25 0110 0 10110 91.67 122.22 73.33 36.67 center +/- 0.25 0110 0 10111 92.50 123.33 74.00 37.00 center +/- 0.25 0110 0 11000 100.00 100.00 66.67 33.33 down sp 0-0.5 % 0110 0 11001 101.00 101.00 67.33 33.67 center +/- 0.25 0110 0 11010 103.00 103.00 68.67 34.33 center +/- 0.25 0110 0 11011 105.00 105.00 70.00 35.00 center +/- 0.25 0110 0 11100 107.00 107.00 71.33 35.67 center +/- 0.25 0110 0 11101 109.00 109.00 72.67 36.33 center +/- 0.25 0110 0 11110 110.00 110.00 73.33 36.67 center +/- 0.25 0110 0 11111 111.00 111.00 74.00 37.00 center +/- 0.25
18 integrated circuit systems, inc. ics953002 0924?11/18/09 table 1a. cpu pll1 turbo rom (continued) fs4 fs3 fsl2 fsl1 fsl0 cpufs4 cpufs3 cpufs2 cpufs1 cpufs0 cpu pci-ex agp pci spreading b0b4 b0b3 b0b2 b0b1 b0b0 b1bit4 b1bit3 b1bit2 b1bit1 b1bit0 mhz (default) (default) (default) % 0110 1 00000 n/a n/a n/a n/a down s p 0-0.5 % 0110 1 00001 n/a n/a n/a n/a center +/- 0.25 0110 1 00010 n/a n/a n/a n/a center +/- 0.25 0110 1 00011 n/a n/a n/a n/a center +/- 0.25 0110 1 00100 n/a n/a n/a n/a center +/- 0.25 0110 1 00101 n/a n/a n/a n/a center +/- 0.25 0110 1 00110 n/a n/a n/a n/a center +/- 0.25 0110 1 00111 n/a n/a n/a n/a center +/- 0.25 0110 1 01000 133.33 100.00 66.67 33.33 down s p 0-0.5 % 0110 1 01001 134.67 101.00 67.33 33.67 center +/- 0.25 0110 1 01010 137.33 103.00 68.67 34.33 center +/- 0.25 0110 1 01011 140.00 105.00 70.00 35.00 center +/- 0.25 0110 1 01100 142.67 107.00 71.33 35.67 center +/- 0.25 0110 1 01101 145.33 109.00 72.67 36.33 center +/- 0.25 0110 1 01110 146.67 110.00 73.33 36.67 center +/- 0.25 0110 1 01111 148.00 111.00 74.00 37.00 center +/- 0.25 0110 1 10000 111.11 111.11 66.67 33.33 down sp 0-0.5 % 0110 1 10001 112.22 112.22 67.33 33.67 center +/- 0.25 0110 1 10010 114.44 114.44 68.67 34.33 center +/- 0.25 0110 1 10011 116.67 116.67 70.00 35.00 center +/- 0.25 0110 1 10100 118.89 118.89 71.33 35.67 center +/- 0.25 0110 1 10101 121.11 121.11 72.67 36.33 center +/- 0.25 0110 1 10110 122.22 122.22 73.33 36.67 center +/- 0.25 0110 1 10111 123.33 123.33 74.00 37.00 center +/- 0.25 0110 1 11000 133.33 100.00 66.67 33.33 down sp 0-0.5 % 0110 1 11001 134.67 101.00 67.33 33.67 center +/- 0.25 0110 1 11010 137.33 103.00 68.67 34.33 center +/- 0.25 0110 1 11011 140.00 105.00 70.00 35.00 center +/- 0.25 0110 1 11100 142.67 107.00 71.33 35.67 center +/- 0.25 0110 1 11101 145.33 109.00 72.67 36.33 center +/- 0.25 0110 1 11110 146.67 110.00 73.33 36.67 center +/- 0.25 0110 1 11111 148.00 111.00 74.00 37.00 center +/- 0.25
19 integrated circuit systems, inc. ics953002 0924?11/18/09 table 1a. cpu pll1 turbo rom (continued) fs4 fs3 fsl2 fsl1 fsl0 cpufs4 cpufs3 cpufs2 cpufs1 cpufs0 cpu pci-ex agp pci spreading b0b4 b0b3 b0b2 b0b1 b0b0 b1bit4 b1bit3 b1bit2 b1bit1 b1bit0 mhz (default) (default) (default) % 0111 0 00000 n/a n/a n/a n/a down s p 0-0.5 % 0111 0 00001 n/a n/a n/a n/a center +/- 0.25 0111 0 00010 n/a n/a n/a n/a center +/- 0.25 0111 0 00011 n/a n/a n/a n/a center +/- 0.25 0111 0 00100 n/a n/a n/a n/a center +/- 0.25 0111 0 00101 n/a n/a n/a n/a center +/- 0.25 0111 0 00110 n/a n/a n/a n/a center +/- 0.25 0111 0 00111 n/a n/a n/a n/a center +/- 0.25 0111 0 01000 200.00 100.00 66.67 33.33 down s p 0-0.5 % 0111 0 01001 202.00 101.00 67.33 33.67 center +/- 0.25 0111 0 01010 206.00 103.00 68.67 34.33 center +/- 0.25 0111 0 01011 210.00 105.00 70.00 35.00 center +/- 0.25 0111 0 01100 214.00 107.00 71.33 35.67 center +/- 0.25 0111 0 01101 218.00 109.00 72.67 36.33 center +/- 0.25 0111 0 01110 220.00 110.00 73.33 36.67 center +/- 0.25 0111 0 01111 222.00 111.00 74.00 37.00 center +/- 0.25 0111 0 10000 166.67 111.11 66.67 33.33 down sp 0-0.5 % 0111 0 10001 168.33 112.22 67.33 33.67 center +/- 0.25 0111 0 10010 171.66 114.44 68.67 34.33 center +/- 0.25 0111 0 10011 175.00 116.67 70.00 35.00 center +/- 0.25 0111 0 10100 178.33 118.89 71.33 35.67 center +/- 0.25 0111 0 10101 181.66 121.11 72.67 36.33 center +/- 0.25 0111 0 10110 183.33 122.22 73.33 36.67 center +/- 0.25 0111 0 10111 185.00 123.33 74.00 37.00 center +/- 0.25 0111 0 11000 200.00 100.00 66.67 33.33 down sp 0-0.5 % 0111 0 11001 202.00 101.00 67.33 33.67 center +/- 0.25 0111 0 11010 206.00 103.00 68.67 34.33 center +/- 0.25 0111 0 11011 210.00 105.00 70.00 35.00 center +/- 0.25 0111 0 11100 214.00 107.00 71.33 35.67 center +/- 0.25 0111 0 11101 218.00 109.00 72.67 36.33 center +/- 0.25 0111 0 11110 220.00 110.00 73.33 36.67 center +/- 0.25 0111 0 11111 222.00 111.00 74.00 37.00 center +/- 0.25
20 integrated circuit systems, inc. ics953002 0924?11/18/09 table 1a. cpu pll1 turbo rom (continued) fs4 fs3 fsl2 fsl1 fsl0 cpufs4 cpufs3 cpufs2 cpufs1 cpufs0 cpu pci-ex agp pci spreading b0b4 b0b3 b0b2 b0b1 b0b0 b1bit4 b1bit3 b1bit2 b1bit1 b1bit0 mhz (default) (default) (default) % 0111 1 00000 n/a n/a n/a n/a down s p 0-0.5 % 0111 1 00001 n/a n/a n/a n/a center +/- 0.25 0111 1 00010 n/a n/a n/a n/a center +/- 0.25 0111 1 00011 n/a n/a n/a n/a center +/- 0.25 0111 1 00100 n/a n/a n/a n/a center +/- 0.25 0111 1 00101 n/a n/a n/a n/a center +/- 0.25 0111 1 00110 n/a n/a n/a n/a center +/- 0.25 0111 1 00111 n/a n/a n/a n/a center +/- 0.25 0111 1 01000 200.00 100.00 66.67 33.33 down s p 0-0.5 % 0111 1 01001 202.00 101.00 67.33 33.67 center +/- 0.25 0111 1 01010 206.00 103.00 68.67 34.33 center +/- 0.25 0111 1 01011 210.00 105.00 70.00 35.00 center +/- 0.25 0111 1 01100 214.00 107.00 71.33 35.67 center +/- 0.25 0111 1 01101 218.00 109.00 72.67 36.33 center +/- 0.25 0111 1 01110 220.00 110.00 73.33 36.67 center +/- 0.25 0111 1 01111 222.00 111.00 74.00 37.00 center +/- 0.25 0111 1 10000 166.67 111.11 66.67 33.33 down sp 0-0.5 % 0111 1 10001 168.33 112.22 67.33 33.67 center +/- 0.25 0111 1 10010 171.66 114.44 68.67 34.33 center +/- 0.25 0111 1 10011 175.00 116.67 70.00 35.00 center +/- 0.25 0111 1 10100 178.33 118.89 71.33 35.67 center +/- 0.25 0111 1 10101 181.66 121.11 72.67 36.33 center +/- 0.25 0111 1 10110 183.33 122.22 73.33 36.67 center +/- 0.25 0111 1 10111 185.00 123.33 74.00 37.00 center +/- 0.25 0111 1 11000 200.00 100.00 66.67 33.33 down sp 0-0.5 % 0111 1 11001 202.00 101.00 67.33 33.67 center +/- 0.25 0111 1 11010 206.00 103.00 68.67 34.33 center +/- 0.25 0111 1 11011 210.00 105.00 70.00 35.00 center +/- 0.25 0111 1 11100 214.00 107.00 71.33 35.67 center +/- 0.25 0111 1 11101 218.00 109.00 72.67 36.33 center +/- 0.25 0111 1 11110 220.00 110.00 73.33 36.67 center +/- 0.25 0111 1 11111 222.00 111.00 74.00 37.00 center +/- 0.25 b0b4 b0b3 b0b2 pci-ex agp pci fs4 fs3 fsl2 b5b6 = 1 b5b7 = 1 b5b7=1 0 0 0 100 66.66 33.33 0 0 1 100 66.66 33.33 0 1 0 100 66.66 33.33 011 102.00 68.00 34.00 100 102.00 68.00 34.00 101 102.00 68.00 34.00 1 1 0 100 66.66 33.33 1 1 1 100 66.66 33.33 center sp +/- 0.25 center sp +/- 0.25 0 to -0.5% down center sp +/- 0.25 center sp +/- 0.25 center sp +/- 0.25 spread % 0 to -0.5% down 0 to -0.5% down table 1b. pll2 agp/pci/src/pci-ex select
21 integrated circuit systems, inc. ics953002 0924?11/18/09 general i 2 c serial interface information for the ics953002 how to write: ? controller (host) sends a start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) sends the data byte count = x ics clock will acknowledge controller (host) starts sending byte n through byte n + x -1 ics clock will acknowledge each byte one at a time controller (host) sends a stop bit how to read: controller (host) will send start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) will send a separate start bit. controller (host) sends the read address d3 (h) ics clock will acknowledge ics clock will send the data byte count = x ics clock sends byte n + x -1 ics clock sends byte 0 through byte x (if x (h) was written to byte 8) . controller (host) will need to acknowledge each byte controllor (host) will send a not acknowledge bit controller (host) will send a stop bit ics (slave/receiver) t wr ack ack ack ack ack p stop bit x byte index block write operation slave address d2 (h) beginning byte = n write start bit controller (host) byte n + x - 1 data byte count = x beginning byte n t start bit wr write rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge pstop bit slave address d3 (h) index block read operation slave address d2 (h) beginning byte = n ack ack data byte count = x ack ics (slave/receiver) controller (host) x byte ack ack
22 integrated circuit systems, inc. ics953002 0924?11/18/09 i 2 c table: device control register bit 7 fs source frequency h/w iic select rw 0 bit 6 reserved reserved rw 1 bit 5 rod reset on demand rw 0 bit 4 fs4 freq/div sel bit 4 rw latch bit 3 fs3 freq/div sel bit 3 rw latch bit 2 fsl2 freq/div sel bit 2 rw latch bit 1 fsl1 freq/div sel bit 1 rw latch bit 0 fsl0 freq/div sel bit 0 rw latch i 2 c table: device control register bit 7 ss_en1 pll1 spread enable rw 1 bit 6 ss_en2 pll2 spread enable rw 1 bit 5 m/n enable bit m/n programming enable bit rw 0 bit 4 cpufs4 pll1 vco sel b4 rw x bit 3 cpufs3 pll1 vco sel b3 rw x bit 2 cpufs2 pll1 vco sel b2 rw 0 bit 1 cpufs1 pll1 vco sel b1 rw 0 bit 0 cpufs0 pll1 vco sel b0 rw 0 b1b[4:3] = 00 is invalid i 2 c table: output control register bit 7 ref0 output control rw 1 bit 6 ref1 output control rw 1 bit 5 pciclk0 output control rw 1 bit 4 pciclk1 output control rw 1 bit 3 pciclk2 output control rw 1 bit 2 pciclk3 output control rw 1 bit 1 pciclk4 output control rw 1 bit 0 pciclk5 output control rw 1 i 2 c table: output control register bit 7 48mhz output control rw 1 bit 6 24_48mhz output control rw 1 bit 5 3v66_2 output control rw 1 bit 4 3v66_1 output control rw 1 bit 3 3v66_0 output control rw 1 bit 2 - sel24_48mhz output select rw latch bit 1 itp_en output select rw latch bit 0 mode 0 output select rw latch enable disable enable enable disable disable disable disable enable enable cpu_stop/pci_p ciex_stop cpuclkt/c2 48mhz 24mhz - - - - - pwd - name control function type 0 - - - byte 3 - - - name 1 enable disable disable name type control function type pwd 1 01 latch inputs off enable - - - pwd pwd - byte 1 pin # - - - - - pin # - - name - - - byte 2 pin # - - - type byte 0 pin # - control function control function iic on on -- disable enable see table 1b: pll2 agp/pci frequency selection table off 0 disable disable pciexclkt/c5 disable 1 pciexclkt/c0 enable disable enable enable enable disable disable disable enable see table 1a: pll1 rom vco frequency selection table 0 enable - enable
23 integrated circuit systems, inc. ics953002 0924?11/18/09 i 2 c table: out p ut control re g ister bit 7 pciexclkt/c5 output control rw 1 bit 6 pciexclkt/c4 output control rw 1 bit 5 pciexclkt/c3 output control rw 1 bit 4 pciexclkt/c2 output control rw 1 bit 3 pciexclkt/c1 output control rw 1 bit 2 cpuclk2/pciex0 output control rw 1 bit 1 cpuclkt/c1 output control rw 1 bit 0 cpuclkt/c0 output control rw 1 i 2 c table: device control register bit 7 agp/pci pll cntrl agp/pci pll source rw 0 bit 6 pciex pll cntrl pciex pll source rw 0 bit 5 reserved reserved rw 1 bit 4 reserved reserved rw 1 bit 3 async1 rw 0 bit 2 async0 rw 0 bit 1 reserved reserved rw 1 bit 0 reserved reserved rw 1 i 2 c table: reserved register bit 7 reserved reserved rw 0 bit 6 reserved reserved rw 0 bit 5 reserved reserved rw 0 bit 4 reserved reserved rw 0 bit 3 reserved reserved rw 0 bit 2 reserved reserved rw 0 bit 1 reserved reserved rw 0 bit 0 reserved reserved rw 0 i 2 c table: vendor id register bit 7 revid3 revision id r 0 bit 6 revid2 revision id r 0 bit 5 revid1 revision id r 0 bit 4 revid0 revision id r 0 bit 3 vid3 vendor id r 0 bit 2 vid2 vendor id r 0 bit 1 vid1 vendor id r 0 bit 0 vid0 vendor id r 1 -- - -- - - - - - - - - - - - -- - 01 = 66.0/33.0 enable pll1 pll2 disable 0 enable - - - - - - - - - - - - - byte 6 pin # - - - pin # - name - - - - - - byte 4 - pin # - - - name control function control function 0 - 0001 = ics type type type name 1pwd 1 01 type - pwd pwd pwd byte 7 - - - - - name - byte 5 - - - - pin # control function control function 3v66/pci async freq prog bits disable disable - - - enable disable disable disable - 00 = pll1/2 10 = 75.4/37.7 pll2 11 = 88.0/44.0 - disable pll1 - 0 - - - enable disable enable -- -- enable enable enable 1
24 integrated circuit systems, inc. ics953002 0924?11/18/09 i 2 c table: byte count register bit 7 bc7 rw 0 bit 6 bc6 rw 0 bit 5 bc5 rw 0 bit 4 bc4 rw 0 bit 3 bc3 rw 1 bit 2 bc2 rw 1 bit 1 bc1 rw 1 bit 0 bc0 rw 1 i 2 c table: wd time control register bit 7 wden watchdog enable rw 0 bit 6 wdsen watchdog soft reset enable rw 0 bit 5 wd alarm status wd alarm status r x bit 4 wd soft status wd soft reset status r x bit 3 wdtctrl watch dog time base control rw 0 bit 2 wd2 wd timer bit 2 rw 1 bit 1 wd1 wd timer bit 1 rw 1 bit 0 wd0 wd timer bit 0 rw 1 i 2 c table: m/n programming & wd safe frequency control register bit 7 reserved reserved rw 1 bit 6 reserved reserved rw 1 bit 5 wd safe freq source wd safe freq source rw 0 bit 4 wd sf4 rw 0 bit 3 wd sf3 rw 0 bit 2 wd sf2 rw 0 bit 1 wd sf1 rw 0 bit 0 wd sf0 rw 0 i 2 c table: pll1 frequency control register bit 7 n div8 n divider prog bit 8 rw x bit 6 n div9 n divider prog bit 9 rw x bit 5 m div5 rw x bit 4 m div4 rw x bit 3 m div3 rw x bit 2 m div2 rw x bit 1 m div1 rw x bit 0 m div0 rw x name byte 8 pin # - - watch dog safe freq programming bits - - - - - - - byte 9 pin # name - pwd m divider programming bits type type pwd pwd type 01 1 pwd - byte count programming b(7:0) - - - - - - - type - - - - byte 10 pin # control function name - byte 11 pin # name - - - - - - - - - control function control function control function 0 alarm the decimal representation of m and n divier in byte 11 and 12 will configure the pll1 vco frequency. default at power up = latch-in or byte 0 rom table. vco frequency = 14.318 x [ndiv(9:0)+8] / [mdiv(5:0)+2] disable enable 1160ms base writing to this register will configure how many bytes will be read back, default is 0f = 15 bytes. writing to these bit will configure the safe frequency as byte0 bit (4:0). - - b10b(4:0) these bits represent x*290ms (or 1.16s) the watchdog timer waits before it goes to alarm mode. default is 7 x 290ms = 2s. 290ms base 01 disable enable 01 normal normal latch inputs - - alarm
25 integrated circuit systems, inc. ics953002 0924?11/18/09 i 2 c table: pll1 frequency control register bit 7 n div7 rw x bit 6 n div6 rw x bit 5 n div5 rw x bit 4 n div4 rw x bit 3 n div3 rw x bit 2 n div2 rw x bit 1 n div1 rw x bit 0 n div0 rw x i 2 c table: pll1 spread spectrum control register bit 7 ssp7 rw x bit 6 ssp6 rw x bit 5 ssp5 rw x bit 4 ssp4 rw x bit 3 ssp3 rw x bit 2 ssp2 rw x bit 1 ssp1 rw x bit 0 ssp0 rw x i 2 c table: pll1 spread spectrum control register bit 7 reserved reserved r 0 bit 6 ssp14 rw x bit 5 ssp13 rw x bit 4 ssp12 rw x bit 3 ssp11 rw x bit 2 ssp10 rw x bit 1 ssp9 rw x bit 0 ssp8 rw x i 2 c table: output divider control register bit 7 cpudiv3 rw 0000:/2 0100:/4 1000:/8 1100:/16 x bit 6 cpudiv2 rw 0001:/3 0101:/6 1001:/12 1101:/24 x bit 5 cpudiv1 rw 0010:/5 0110:/10 1010:/20 1110:/40 x bit 4 cpudiv0 rw 0011:/7 0111:/14 1011:/28 1111:/56 x bit 3 agp/pcidiv3 rw 0000:/2 0100:/4 1000:/8 1100:/16 x bit 2 agp/pcidiv2 rw 0001:/3 0101:/6 1001:/12 1101:/24 x bit 1 agp/pcidiv1 rw 0010:/5 0110:/10 1010:/20 1110:/40 x bit 0 agp/pcidiv0 rw 0011:/7 0111:/14 1011:/28 1111:/56 x agp/pci divider ratio programmaing bits pll2 pwd pwd byte 12 pin # name - - name type type - n divider programming b(7:0) - - - - - control function - - - - byte 13 pin # - - pwd - byte 14 pin # name type control function -- 0 - - - - - - - - - spread spectrum programming b(14:8) spread spectrum programming b(7:0) control function 0 1 01 these spread spectrum bits in byte 13 and 14 will program the spread pecentage of pll1 the decimal representation of m and n divier in byte 11 and 12 will configure the pll1 vco frequency. default at power up = latch-in or byte 0 rom table. vco frequency = 14.318 x [ndiv(9:0)+8] / [mdiv(5:0)+2] pwd byte 15 pin # name control function 0 1 - - - - - - - - these spread spectrum bits in byte 13 and 14 will program the spread pecentage of pll1 1 cpu divider ratio programmaing bits type
26 integrated circuit systems, inc. ics953002 0924?11/18/09 i 2 c table: out p ut divider control re g ister bit 7 reserved reserved rw 1 bit 6 reserved reserved rw 1 bit 5 reserved reserved rw 1 bit 4 reserved reserved rw 1 bit 3 agp/pcidiv3 rw 0000:/4 0100:/8 1000:/16 1100:/32 x bit 2 agp/pcidiv2 rw 0001:/3 0101:/6 1001:/12 1101:/24 x bit 1 agp/pcidiv1 rw 0010:/5 0110:/10 1010:/20 1110:/40 x bit 0 agp/pcidiv0 rw 0011:/9 0111:/18 1011:/36 1111:/72 x i 2 c table: pll2 frequency control register bit 7 n div8 n divider prog bit 8 rw x bit 6 n div9 n divider prog bit 9 rw x bit 5 m div5 rw x bit 4 m div4 rw x bit 3 m div3 rw x bit 2 m div2 rw x bit 1 m div1 rw x bit 0 m div0 rw x i 2 c table: pll2 frequency control register bit 7 n div7 rw x bit 6 n div6 rw x bit 5 n div5 rw x bit 4 n div4 rw x bit 3 n div3 rw x bit 2 n div2 rw x bit 1 n div1 rw x bit 0 n div0 rw x i 2 c table: pll2 spread spectrum control register bit 7 ssp7 rw x bit 6 ssp6 rw x bit 5 ssp5 rw x bit 4 ssp4 rw x bit 3 ssp3 rw x bit 2 ssp2 rw x bit 1 ssp1 rw x bit 0 ssp0 rw x 1 -- - - - the decimal representation of m and n divier in byte 17 and 18 will configure the pll2 vco frequency. default at power up = latch-in or byte 0 rom table. vco frequency = 14.318 x [ndiv(9:0)+8] / [mdiv(5:0)+2] m divider programming bits type 0 1 0 byte 16 pin # name control function - - - - - - - - - - 1 - - - - - n divider programming b(7:0) byte 18 - - - 0 byte 17 pin # name control function - - the decimal representation of m and n divier in byte 17 and 18 will configure the pll2 vco frequency. default at power up = latch-in or byte 0 rom table. vco frequency = 14.318 x [ndiv(9:0)+8] / [mdiv(5:0)+2] - - - - - - - pwd pwd pwd name control function - type agp/pci divider ratio programmaing bits pll1 - - - - - - byte 19 pin # pin # - name control function type type pwd 01 these spread spectrum bits in byte 19 and 20 will program the spread pecentage of pll2 spread spectrum programming b(7:0)
27 integrated circuit systems, inc. ics953002 0924?11/18/09 i 2 c table: pll2 spread spectrum control register bit 7 reserved reserved r 0 bit 6 ssp14 rw x bit 5 ssp13 rw x bit 4 ssp12 rw x bit 3 ssp11 rw x bit 2 ssp10 rw x bit 1 ssp9 rw x bit 0 ssp8 rw x -- spread spectrum programming b(14:8) these spread spectrum bits in byte 19 and 20 will program the spread pecentage of pll2 pwd 01 name control function type - - - byte 20 pin # - - - - -
28 integrated circuit systems, inc. ics953002 0924?11/18/09 fig. 1 shared pin operation - input/output pins the i/o pins designated by (input/output) serve as dual signal functions to the device. during initial power-up, they act as input pins. the logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. at the end of power-on reset, (see ac characteristics for timing values), the device changes the mode of operations for these pins to an output function. in this mode the pins produce the specified buffered clocks to external loads. to program (load) the internal configuration register for these pins, a resistor is connected to either the vdd (logic 1) power supply or the gnd (logic 0) voltage potential. a 10 kilohm (10k) resistor is used to provide both the solid cmos programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. via to vdd clock trace to load series term. res. programming header via to gnd device pad 2k 8.2k figure 1 shows a means of implementing this function when a switch or 2 pin header is used. with no jumper is installed the pin will be pulled high. with the jumper in place the pin will be pulled low. if programmability is not necessary, than only a single resistor is necessary. the programming resistors should be located close to the series termination resistor to minimize the current loop area. it is more important to locate the series termination resistor close to the driver than the programming resistor.
29 integrated circuit systems, inc. ics953002 0924?11/18/09 absolute maximum rating parameter symbol conditions min typ max units notes 3.3v core supply voltage vdd_a - v dd + 0.5v v 1 3.3v logic input supply voltage vdd_in - gnd - 0.5 v dd + 0.5v v 1 storage temperature ts - -65 150 c 1 ambient operating temp tambient - 070c 1 case temperature tcase - 115 c 1 input esd protection hbm esd prot - 2000 v 1 1 guaranteed by design and characterization, not 100% tested in production. electrical characteristics - input/supply/common output parameters parameter symbol conditions* min typ max units notes input high voltage v ih 3.3 v +/-5% 2 v dd + 0.3 v 1 input low voltage v il 3.3 v +/-5% v ss - 0.3 0.8 v 1 input high current i ih v in = v dd -5 5 ua 1 i il1 v in = 0 v; inputs with no pull-up resistors -5 ua 1 i il2 v in = 0 v; inputs with pull-up resistors -200 ua 1 low threshold input- high voltage v ih_fs 3.3 v +/-5% 0.7 v dd + 0.3 v 1 low threshold input- low voltage v il_fs 3.3 v +/-5% v ss - 0.3 0.35 v 1 operating supply current i dd3.3op full active, c l = full load; 350 ma 1 operating current i dd3.3op all outputs driven 400 ma 1 all diff pairs driven 70 ma 1 all differential pairs tri-stated 12 ma 1 input frequency f i v dd = 3.3 v 14.31818 mhz 2 pin inductance l p in 7nh1 c in logic inputs 5 pf 1 c out output pin capacitance 6 pf 1 c inx x1 & x2 pins 5 pf 1 clk stabiliz ation t stab from v dd power-up or de- assertion of pd# to 1st clock 1.8 ms 1 modulation frequency triangular modulation 30 33 khz 1 tdrive_pd# cpu output enable after pd# de-assertion 300 us 1 tfall_pd# pd# fall time of 5 ns 1 trise_pd# pd# rise time of 5 ns 1 smbus voltage v dd 2.7 5.5 v 1 low-level output voltage v ol @ i pullup 0.4 v 1 current sinking at v ol = 0.4 v i pullup 4ma1 sclk/sdata clock/data rise time t ri2c (max vil - 0.15) to (min vih + 0.15) 1000 ns 1 sclk/sdata clock/data fall time t fi2c (min vih + 0.15) to (max vil - 0.15) 300 ns 1 *ta = 0 - 70c; supply voltage vdd = 3.3 v +/-5% 1 guaranteed by design and characterization, not 100% tested in production. 2 input frequency should be measured at the ref pin and tuned to ideal 14.31818mhz to meet ppm frequency accuracy on pll outputs. input low current powerdown current i dd3.3pd input capacitance
30 integrated circuit systems, inc. ics953002 0924?11/18/09 electrical characteristics - cpuclkt/c -- 0.7v current mode differential pair parameter symbol conditions* min typ max units notes current source output impedance zo v o = v x 3000 ? 1 voltage high vhigh 660 850 mv 1,3 voltage low vlow -150 150 mv 1,3 max voltage vovs 1150 mv 1 min voltage vuds -300 mv 1 crossing voltage (abs) vx(abs) 250 550 mv 1 crossing voltage (var) d-vx variation of crossing over all ed g es 140 mv 1 long accuracy ppm see tperiod min-max values -300 300 ppm 1,2 400mhz nominal 2.4993 2.5008 ns 2 400mhz spread 2.4993 2.5133 ns 2 333.33mhz nominal 2.9991 3.0009 ns 2 333.33mhz spread 2.9991 3.016 ns 2 266.66mhz nominal 3.7489 3.7511 ns 2 266.66mhz spread 3.7489 3.77 ns 2 200mhz nominal 4.9985 5.0015 ns 2 200mhz spread 4.9985 5.0266 ns 2 166.66mhz nominal 5.9982 6.0018 ns 2 166.66mhz spread 5.9982 6.0320 ns 2 133.33mhz nominal 7.4978 7.5023 ns 2 133.33mhz spread 7.4978 7.5400 ns 2 100.00mhz nominal 9.9970 10.0030 ns 2 100.00mhz spread 9.9970 10.0533 ns 2 400mhz nominal/spread 2.4143 ns 1,2 333.33mhz nominal/spread 2.9141 ns 1,2 266.66mhz nominal/spread 3.6639 ns 1,2 200mhz nominal/spread 4.8735 ns 1,2 166.66mhz nominal/spread 5.8732 ns 1,2 133.33mhz nominal/spread 7.3728 ns 1,2 100.00mhz nominal/spread 9.8720 ns 1,2 rise time t r v ol = 0.175v, v oh = 0.525v 175 700 ps 1 fall time t f v oh = 0.525v v ol = 0.175v 175 700 ps 1 rise time variation d-t r v ol = 0.175v, v oh = 0.525v 125 ps 1 fall time variation d-t f v oh = 0.525v v ol = 0.175v 125 ps 1 duty cycle d t3 measurement from differential wavefrom 45 55 % 1 skew t sk3 cpu(1:0), v t = 50% 100 ps 1 skew t sk4 cpu(1:0) to cpu2_itp, v t = 50% 150 ps 1 jitter, cycle to cycle t jcyc-cyc measurement from differential wavefrom ( cpu2_itp ) 125 ps 1 jitter, cycle to cycle t jcyc-cyc measurement from differential wavefrom , ( cpu ( 1:0 )) 85 ps 1 *t a = 0 - 70c; v dd = 3.3 v +/-5%; c l =2pf, r s =33.2 ? , r p =49.9 ?, ref = 475? 1 guaranteed by design and characterization, not 100% tested in production. 2 all long term accuracy and clock period specifications are guaranteed assuming that refout is at 14.31818mhz 3 i ref = v dd /(3xr r ). for r r = 475 ? (1%), i ref = 2.32ma. i oh = 6 x i ref and v oh = 0.7v @ z o =50 ? . statistical measurement on sin g le ended signal measurement on single ended signal using absolute value. average period tperiod absolute min period t absmin
31 integrated circuit systems, inc. ics953002 0924?11/18/09 electrical characteristics - src/sata/pciex 0.7v current mode differential pair parameter symbol conditions* min typ max units notes current source output impedance zo v o = v x 3000 ? 1 voltage high vhigh 660 850 mv 1,3 voltage low vlow -150 150 mv 1,3 max voltage vovs 1150 mv 1 min voltage vuds -300 mv 1 crossing voltage (abs) vx(abs) 250 550 mv 1 crossing voltage (var) d-vx variation of crossing over all ed g es 140 mv 1 long accuracy ppm see tperiod min-max values -300 300 ppm 1,2 100.00mhz nominal 9.9970 10.0030 ns 2 100.00mhz spread 9.9970 10.0533 ns 2 absolute min period tabsmin 100.00mhz nominal/spread 9.8720 ns 1,2 rise time t r v ol = 0.175v, v oh = 0.525v 175 700 ps 1 fall time t f v oh = 0.525v v ol = 0.175v 175 700 ps 1 rise time variation d-t r v ol = 0.175v, v oh = 0.525v 125 ps 1 fall time variation d-t f v oh = 0.525v v ol = 0.175v 125 ps 1 duty cycle d t3 measurement from differential wavefrom 45 55 % 1 skew t sk3 v t = 50% 250 ps 1 jitter, cycle to cycle t jcyc-cyc measurement from differential wavefrom 125 ps 1 *t a = 0 - 70c; v dd = 3.3 v +/-5%; c l =2pf, r s =33.2 ? , r p =49.9 ?, ref = 475? 1 guaranteed by design and characterization, not 100% tested in production. 2 all long term accuracy and clock period specifications are guaranteed assuming that refout is at 14.31818mhz 3 i ref = v dd /(3xr r ). for r r = 475 ? (1%), i ref = 2.32ma. i oh = 6 x i ref and v oh = 0.7v @ z o =50 ? . statistical measurement on sin g le ended signal measurement on single ended signal using absolute value. average period tperiod electrical characteristics - pciclk/pciclk_f parameter symbol conditions* min typ max units notes output impedance r dsp v o = v dd *(0.5) 12 55 ? 1 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.55 v 1 v oh @min = 1.0 v -33 ma 1 v oh @max = 3.135 v -33 ma 1 v ol @ min = 1.95 v 30 ma 1 v ol @ max = 0.4 v 38 ma 1 edge rate t slewr/f rising/falling edge rate 1 4 v/ns 1 rise time t r v ol = 0.4 v, v oh = 2.4 v 0.5 2 ns 1 fall time t f v oh = 2.4 v, v ol = 0.4 v 0.5 2 ns 1 duty cycle d t1 v t = 1.5 v 45 55 %1 group skew t skew v t = 1.5 v 500 ps 1 jitter, cycle to cycle t jcyc-cyc v t = 1.5 v 500 ps 1 *ta = 0 - 70c; supply voltage vdd = 3.3 v +/-5%, cl = 20 pf with rs = 7 ? (unless otherwise specified) 1 guaranteed b y desi g n and characterization, not 100% tested in p roduction. output high current i oh output low current i ol
32 integrated circuit systems, inc. ics953002 0924?11/18/09 electrical characteristics - 48mhz/usb48mhz/24_48mhz parameter symbol conditions* min typ max units notes long accuracy ppm see tperiod min-max values -100 100 ppm 1 clock period t period 48.00mhz output nominal 20.8313 20.8354 ns output impedance r dsp v o = v dd *(0.5) 12 55 ? 1 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.55 v 1 v oh @min = 1.0 v -33 ma 1 v oh @max = 3.135 v -33 ma 1 v ol @ min = 1.95 v 30 ma 1 v ol @ max = 0.4 v 38 ma 1 edge rate t slewr/f rising/falling edge rate 1 4 v/ns 1 edge rate t slewr/f_usb usb48 rising/falling edge rate 1 2 v/ns 1 rise time t r v ol = 0.4 v, v oh = 2.4 v 0.5 2 ns 1 fall time t f v oh = 2.4 v, v ol = 0.4 v 0.5 2 ns 1 rise time t r_usb v ol = 0.4 v, v oh = 2.4 v 12ns 1 fall time t f_usb v oh = 2.4 v, v ol = 0.4 v 12ns 1 duty cycle d t1 v t = 1.5 v 45 55 %1 group skew t skew v t = 1.5 v 250 ps 1 jitter, cycle to cycle t jcyc-cyc v t = 1.5 v 500 ps 1 *ta = 0 - 70c; supply voltage vdd = 3.3 v +/-5%, cl = 20 pf with rs = 7 ? (rs is used in usb48mhz test only) 1 guaranteed b y desi g n and characterization, not 100% tested in p roduction. output high current i oh output low current i ol electrical characteristics - agpclk/3v66 parameter symbol conditions* min typ max units notes output impedance r dsp v o = v dd *(0.5) 12 55 ? 1 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.55 v 1 v oh @min = 1.0 v -33 ma 1 v oh @max = 3.135 v -33 ma 1 v ol @ min = 1.95 v 30 ma 1 v ol @ max = 0.4 v 38 ma 1 rise time t r v ol = 0.4 v, v oh = 2.4 v 0.5 2 ns 1 fall time t f v oh = 2.4 v, v ol = 0.4 v 0.5 2 ns 1 duty cycle d t1 v t = 1.5 v 45 55 %1 group skew t skew v t = 1.5 v 150 ps 1 jitter, cycle to cycle t jcyc-cyc v t = 1.5 v 250 ps 1 *ta = 0 - 70c; supply voltage vdd = 3.3 v +/-5%, cl = 10-30 pf (unless otherwise specified) 1 guaranteed b y desi g n and characterization, not 100% tested in p roduction. output low current i ol output high current i oh
33 integrated circuit systems, inc. ics953002 0924?11/18/09 electrical characteristics - ref-14.318mhz parameter symbol conditions min typ max units notes long accuracy ppm see tperiod min-max values -300 300 ppm 1,2 clock period t p eriod 14.318mhz output nominal 69.8270 69.8550 ns 2 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.4 v 1 output high current i oh v oh @min = 1.0 v, v oh @max = 3.135 v -29 -23 ma 1 output low current i ol v ol @min = 1.95 v, v ol @max = 0.4 v 29 27 ma 1 edge rate t slewr/f rising/falling edge rate 1 4 v/ns 1 rise time t r1 v ol = 0.4 v, v oh = 2.4 v 1 2 ns 1 fall time t f1 v oh = 2.4 v, v ol = 0.4 v 1 2 ns 1 skew t sk1 v t = 1.5 v inverted ps 3 duty cycle d t1 v t = 1.5 v 45 55 % 1 jitter t j c y c-c y c v t = 1.5 v 1000 ps 1 *ta = 0 - 70c; supply voltage vdd = 3.3 v +/-5%, cl = 20 pf with rs = 7 ? (rs is used in usb48mhz test only) 1 guaranteed by design and characterization, not 100% tested in production. 2 all long term accuracy and clock period specifications are guaranteed assuming that refout is at 14.31818mhz 3 the ref outputs are inverted with respect to each other. the exact skew value is not critical.
34 integrated circuit systems, inc. ics953002 0924?11/18/09 min max min max a 2.41 2.80 .095 .110 a1 0.20 0.40 .008 .016 b 0.20 0.34 .008 .0135 c 0.13 0.25 .005 .010 d e 10.03 10.68 .395 .420 e1 7.40 7.60 .291 .299 e h 0.38 0.64 .015 .025 l 0.50 1.02 .020 .040 n 0 8 0 8 variations min max min max 56 18.31 18.55 .720 .730 10-0034 reference doc.: jedec publication 95, mo-118 56-lead, 300 mil body, 25 mil, ssop n see variations see variations d mm. d (inch) symbol see variations see variations 0.635 basic 0.025 basic common dimensions in millimeters in inches common dimensions index area index area 12 1 2 n d h x 45 h x 45 e1 e seating plane seating plane a1 a e -c- - c - b .10 (.004) c .10 (.004) c c l ordering information part / order number shipping packaging package temperature 953002CFLF tubes 56-pin ssop 0 to +70 c 953002CFLFt tape and reel 56-pin ssop 0 to +70 c 953002dflf tubes 56-pin ssop 0 to +70 c 953002dflft tape and reel 56-pin ssop 0 to +70 c parts that are ordered with a "lf" suffix to the part number are the pb-free configuration and are rohs compliant.
35 integrated circuit systems, inc. ics953002 0924?11/18/09 revision history rev. issue date description page # 0.1 6/13/2005 1. updated frequency table. 2. updated lf ordering information to rohs compliant. 1, 5-12, 25 0.2 9/1/2005 updated frequency table 5-12 0.3 5/29/2008 added smbus read/write information. 21 0.4 9/26/2008 corrected typos on bytes 15:20 25, 26, 27 a 6/11/2009 moved to final. b 11/18/2009 removed ref skew spec from ds. this spec is not required and is not critical functionality of the device or system. the ref outputs are inverted (180 degrees out of phase) with each other. 33

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